1. Field of the Invention
The present invention relates to a semiconductor memory and a semiconductor device. More particularly, the invention relates to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
Semiconductor memories fall primarily into two categories: volatile memories represented by the RAM (Random Access Memory), and nonvolatile memories exemplified by the ROM (Read Only Memory). The nonvolatile memories are further divided into DRAMs and SRAMs (Static Random Access Memories). The nonvolatile memories include mask ROMs, EPROMs, flash memories, EEPROMs and fuse ROMs.
The DRAM in operation needs to be refreshed constantly because it stores data by keeping the capacitor of each of its memory cells electrically charged. On the other hand, the DRAM is suitable for use as a low-cost large-capacity memory device because the memory cell structure thereof is simple to fabricate.
Because DRAMs store data by keeping the capacitor of each of their memory cells charged, they have the disadvantage of being liable to what is known as soft error. The phenomenon of soft error involves alpha particles being released from the package and/or the wiring and entering the substrate to cause carriers therein. When the carriers thus generated reach any capacitor, they alter the amount of charges in that capacitor, whereby the data of the capacitor is inverted.
Meanwhile, recent years have seen progress in the development of semiconductor devices having the so-called SOI (Silicon On Insulator) structure. This structure comprises transistors and like circuit elements formed on the SOI substrate. When thus structured, the semiconductor device includes an insulating layer in its semiconductor substrate and has a very thin SOI active layer formed over the substrate surface of that insulating layer.
One prominent characteristic of the semiconductor device having the SOI structure is the presence of the very thin active layer. Given that characteristic, it is possible to resolve the problem of soft error with DRAMs to which the SOI structure is applied. It is from that standpoint that attempts to fabricate DRAMs having the SOI structure have been contemplated.
When a DRAM is formed conventionally by use of the SOI structure, the transistors constituting that DRAM are each arranged as described below. FIG. 23 is a cross-sectional view showing a typical constitution of an MOS transistor in a conventional SOI-structure semiconductor device.
Referring to FIG. 23, the MOS transistor comprises a first conductivity type pair of source and drain regions 91, a second conductivity type body region 92, and a second conductivity type gate electrode 93.
This MOS transistor is formed on an SOI substrate 90. The SOI substrate is composed of a silicon substrate 94, an insulating layer 95 and an SOI active layer 96. Inside the SOI active layer 96, a pair of a source and a drain region 91 are formed a predetermined distance apart. Between the two regions is the body region 92.
That is, the body region 92 comes under the gate electrode 93. When the gate electrode 93 is fed with a potential of a predetermined level, a channel is formed within the body region 92.
Numerous units of this type of MOS transistor are used throughout the DRAM. Illustratively, in the peripheral circuits of the DRAM, MOS transistors of different conductivity types are combined to constitute a CMOS circuit and the like.
Where the DRAM is formed by use of the SOI structure, one of two methods may be adopted conventionally to isolate the memory elements such as MOS transistors from one another. One method is an LOCOS (LOCal Oxidation of Silicon) isolation method that utilizes an oxide isolation arrangement; the other method is a field shield isolation method that employs field shield gate electrodes. However, these conventional methods have their share of disadvantages as outlined below.
One advantage of adopting the LOCOS isolation method is its ability to protect the CMOS circuit from a latch-up. But this advantage of the LOCOS isolation method is more than offset by its disadvantage involving the body region 92, located under the gate electrode 93 of each transistor, getting into an electrically floating state. This floating state is caused by the fact that the body region 92 is electrically isolated from the silicon substrate 94 by the insulating layer 95.
With the body region 92 in the floating state, the following troubles arise: the withstanding voltage between the source and the drain is undermined by parasitic bipolar action. There occurs an increased tendency for a leak current to flow between the source and the drain. Furthermore, a kink is generated and the drain current Id--drain voltage Vd characteristic is observed. That is, the operation of the transistors becomes unstable.
One advantage of utilizing the field shield isolation method is that the body region 92 of each transistor has its potential fixed so that the above-mentioned troubles associated with the floating state do not occur. This benefit stems from the fact that all regions in the SOI active layer 96 are in PN junction. However, the field shield isolation method has one distinct disadvantage: a latch-up can occur inside the CMOS circuit.